Technological improvements of silicon based quantum devices for a scalable qubit architecture

Klos, Jan; Bluhm, Jörg (Thesis advisor); Knoch, Joachim (Thesis advisor)

Aachen : RWTH Aachen University (2023)
Dissertation / PhD Thesis

Dissertation, RWTH Aachen University, 2023

Abstract

Gate-defined electron spin quantum bits localized in a silicon-based substrate are an excellent platform for scalable quantum computing systems with outstanding qubit performance metrics such as long coherence times and high manipulation fidelities. However, the confined electron constantly interacts with the semiconductor host-crystal and its charged defects and imperfections on a length scale of tens of nanometers. Hence, technological improvements are necessary to ensure a scalable qubit architecture. In this work, dominant sources of electrostatic potential disorder are identified and used to define technological requirements for improvement. Based on electrostatic simulations of representative quantum devices, charged defects located within the dielectric layers below the metal gate structure have been identified to exhibit a dominating influence on the potential landscape surrounding the qubits. From these three aspects for technological improvements are derived and investigated in more detail in this work, stating (1) the need for a high-density, high process yield, single-layer gate structure with sub-50 nm gate footprint, (2) the minimization of charged defects within the dielectric layers and (3) the quantification of the sub-nanometer influence of quantum chip fabrication on the confining interfaces of a Si/SiGe heterostructure. First, a novel spacer-based gate structure fabrication approach is developed in an academic cleanroom environment and used to fabricate single-layer double quantum dot gate structures with gate widths ranging between 25 nm and 50 nm and SiO2 insulation thickness ranging from 12 nm up to 25 nm. The approach is compatible with industrial CMOS semiconductor fabrication lines and allows high-yield and low variability. Process development is performed by systematic post-process data analysis. In-line process metrology based on top-down SEM measuring the critical dimension in combination with a novel empirical fit-function edge detection algorithm is used to measure process dependent fabrication biases and characterize individual quality parameters along the full fabrication process. Electrical characterization at cryogenic temperatures exhibits suitable metal gate conductivities but suggest to limit gate designs to linear gates. Second, the dielectric material stack is optimized with respect to charged defect concentrations based on impedance spectroscopy of MOS capacitors at room temperature. Minimal concentrations of charge defects of (1.3 ± 0.9) ⋅ 1E11 cm-2 and interface traps of (3.9 ± 1.0) ⋅ 1E10 eV-1cm-2 for a material stack consisting of 5.2 nm CVD SiO2 and 20 nm ALD Al2O3. The resulting potential variation measured at the SiO2/Si interface is as low as (57 ± 3) meV. No systematic advantage for an enhanced dielectric quality based on various deposition processes and material sources has been observed. Third, a state-of-the-art MBE-grown isotopically purified 28Si/Si0.7Ge0.3 heterostructure is investigated using HR-TEM, APT and low-energy ToF-SIMS with sub-nanometer resolution. Post-growth thermal treatment with temperatures exceeding the heterostructure growth temperature increase the interface widths of the 28Si quantum well (QW). Moreover, interface widths vary for Si and Ge with (0.5 ± 0.1) nm and (0.76 ± 0.03) nm at the top interface of the QW, respectively. Ge segregation is identified affecting both QW interfaces by forming a leading edge, locally increasing concentration of natural Si at the top interface, and a Ge trailing edge extending multiple nanometers into the QW at the bottom interface. By comparing with earlier measurements, two conclusions are drawn: First, large valley splittings do not require atomistically sharp QW interfaces and allow some interface width as measured in this work. Second, the increased concentration of 29Si nuclear spins from the leading edge and of Ge from the trailing edge in the QW are not limiting the measured state-of-the-art qubit dephasing times.

Institutions

• Department of Physics [130000]
• Chair of Experimental Physics and Institute of Physics II [132210]